A variety of electronic devices utilize phase and frequency locking systems, commonly called phase locked loops (PLL). In a conventional analog or continuous system phase locked loop, the output signal from a voltage controlled oscillator is subtracted at a summing junction from a reference input signal, and the difference is fed back, typically through a low pass filter, to the control input of the voltage controlled oscillator. The feedback loop serves to reduce the difference between the input signal and the output of the voltage controlled oscillator to zero and to cause the output of the oscillator to track the reference signal. The time required for the system to lock to a new reference signal, the stability of the phase locked loop, and its sensitivity to noise, depends on the dynamics of the loop. Analog phase locked loops have been extensively investigated and developed, and are in common use in communication systems.
More recently, digital phase locked loops (DPLL) have been developed in which all or part of the function of the loop is carried out in a digital computer, e.g., a dedicated microprocessor or a digital signal processor. One common approach to digital phase locked loops is to implement, through digital processing, essentially the same feedback loops which are carried out in an analog phase locked loop. However, a number of differences can exist between a digital or discrete system implementation of a phase locked loop and an analog implementation. For example, in some discrete systems the controlled output signal may be a square wave rather than a sine wave (the latter typically being the form of the input or reference signal). In such cases, phase and frequency lock is considered to occur when the zero crossings of the controlled signal correspond to the zero crossings of the sinusoidal input signal. If the controlled signal is a square wave or quasi-square wave, the phase and frequency of the controlled signal cannot be changed continuously (as could a continuously varying sinusoidal signal); rather, such a signal can only be changed discretely by changing the phase or frequency of a complete cycle, i.e., by changing the period between the zero crossings of the square wave cycle.
One field of application of phase and frequency locked loops, both analog and digital, is in uninterruptible power systems which provide backup power to a critical load if the main AC power system fails. A variety of configurations for uninterruptible power systems (UPS) have been developed. In some types of uninterruptible power systems, typically those used with single phase power, the UPS normally provides the main power system AC line power directly to the load without an intermediate rectification and inversion of the power. In the United States, the single phase line power is typically at 60 Hz and has a sinusoidal waveform. In other countries, particularly European countries, normal line power may be at 50 Hz. In these types of uninterruptible power systems, when the main line power fails, an inverter is turned on to provide power from a DC energy storage device, typically a battery, to provide output power which has a sinusoidal or quasi-sinusoidal waveform. Generally, the power consuming device is suited to use AC power at the same frequency as was supplied from the main power lines. Thus, the UPS must provide power at that frequency. In addition, to avoid momentary disruptions of the power supplied to a critical load when the main AC line power fails, it is desirable to switch over from the line power to backup power through the inverter as quickly as possible, preferably so rapidly that power is not interrupted to the load for half a cycle or less.
Very rapid line power failure detection techniques have been developed which can detect power failure and turn on the inverter to supply backup power to the load within a fraction of a cycle from a time that the power failure was detected. However, if the output power provided from the inverter does not match in frequency and phase the waveform of the AC line power at the time of failure, a substantial disruption or glitch will appear in the waveform of the power provided to the load. Thus, a UPS of this type typically has a local oscillator with a phase locked loop which locks to the frequency and phase of the incoming AC line power. When the line power fails, the local oscillator continues to provide its periodic output signal at the same phase and frequency as the input signal, and the output of the local oscillator can then be used to control an inverter to provide output power which has the same phase and frequency as the original line power.
Conversely, when AC line power is restored, it will be desirable to switch off the inverter and switch back to providing the AC line power to the load without a significant glitch in the waveform of the power supplied to the load. Thus, when AC line power again becomes available, such UPS systems typically lock the local oscillator onto the AC line power signal so that the output of the inverter and the AC line power are in synchrony at the time that the switch-over is made between the inverter power and power from the main AC power lines.
It is generally desirable that the phase locked loop in the UPS (as well as in other applications of phase locked loops) lock on to the reference signal (e.g., 60 Hz line power) as quickly as possible. In addition, if there is a change in the phase or frequency of the reference signal, it is desirable that the phase locked loop respond to it and achieve phase and frequency coherence in the shortest achievable time to avoid the possibility of the AC line power being lost during a point in time when the local oscillator was not in phase and frequency coherence with the reference. Similarly, when AC line power is restored, it is generally desirable that the UPS be able to switch back to providing power from the main power system to the load as quickly as possible, an objective which is limited in part by the speed at which the phase locked loop can reestablish phase and frequency coherence with AC line power reference.
However, a limit may be imposed by the consuming equipment on the rate at which the phase and frequency of the local oscillator may be changed. For example, if power is being supplied by the inverter to a load under the control of the local oscillator, and line power again becomes available, if the local oscillator is changed too rapidly in phase or frequency to try to reach the phase and frequency of the power line waveform, an unacceptable distortion or glitch in the waveforms of the power supplied to the load may occur. Typically, this limitation is expressed as a maximum rate of change of frequency, or frequency "slew rate". Because of these limitations, the phase locked loops in UPS systems are essentially nonlinear, and are typically implemented as a digital phase locked loop utilizing a microprocessor. In such digital phase locked loops, the speed at which the loop can achieve phase and frequency coherence is limited first by the maximum rate of change constraint (e.g., slew rate), and second by the complexity of the signal processing itself. The second limitation may outweigh the first if, for example, the computations required consume more time as they are carried out in the microprocessor than would otherwise be required by the first limitation. As a simple example, if the local oscillator can be changed at discrete points in time corresponding to increments of the present period of the local oscillator, and if the computations required to calculate the change required in the frequency or phase of the local oscillator will require more than one period's worth of time, then the adjustment of the local oscillator will be slowed. Consequently, it would be desirable that the processing of the digital phase locked loop both efficiently control the change in the local oscillator and also that the control algorithm itself does not consume so much processor time that it slows down the adjustment process from what would otherwise be required, or interfere with other tasks performed by the microprocessor.